Nano-Electro-Mechanical Systems (NEMS) integrating electrical and mechanical functionalities on the nanoscale have a wide range of applications, such as automotive, industrial, telecommunication, consumer, medical, aerospace and defense. There is a demand to integrate separate chips with different functionalities (e.g., logic, memory, RF/Optical, NEMS) into a single chip with better performance and lower cost. Since NEMS logic and memory have low power consumption, it is desirable to fabricate NEMS logic and memory on the same chip and even co-integrated with CMOS logic and memory.
FIG. 1 schematically illustrates a conventional semiconductor structure, having a NEMS memory core 101 integrated with a CMOS peripheral circuit 103 on a substrate 105. NEMS memory core 101 is a Fin Flip-flop actuated channel transistor (FinFACT) and CMOS peripheral circuit 103 is an independent-gate (IG) FinFET, with their respective sources 107 and 111 and respective drains 109 and 113 insulated from the substrate 105 by an insulating (e.g., buried oxide) layer 115.
FIG. 2A shows a cross-sectional view taken in the gate-to-gate direction, and FIG. 2B shows a top view, of the semiconductor structure of FIG. 1. In NEMS memory core 101, air gaps 203 exist between fin 205 and two independent gates 207, 207′, allowing fin 205 to move from one gate to another gate via electrostatic force. An air gap 209 also exists between fin 205 and insulating (e.g., BOX) layer 115, and optionally substrate 105.
The mechanical operation states of the FinFACT (i.e., NEMS memory core 101) are depicted in FIG. 2C. In an initial state, no electrostatic force (e.g., bias voltage) is applied to gates G1, G2. An electrostatic force is used to write ‘1’ or ‘0’ into the FinFACT by applying different biases Vg1, Vg2 to the two gates G1, G2. In a pull-up state (bit ‘1’), fin 205 is attracted to the driving gate (e.g., G1). In a pull-down state (bit ‘0’), fin 205 is attracted to the other gate (e.g., G2).
For a read operation, G1 is used as the driving gate to detect a current flowing from a source 107 to a drain 109. When at bit ‘1’, increasing Vg1 causes a significant current to flow through the source 107 and the drain 109. While at bit ‘0’, increasing Vg1 has no significant impact on the current flowing from source 107 to drain 109.
This conventional structure has a few drawbacks. The silicon-on-insulator (SOI) substrate costs substantially more to manufacture than a bulk substrate. In addition, the FinFET and the FinFACT on SOI suffer from a self-heating effect that degrades the FinFET and induces thermal stress to the FinFACT. The fin breaks easily due to the thermal stress, thereby rendering the FinFACT inoperable.
A need therefore exists for methodology for forming a semiconductor structure with a NEMS on a bulk substrate, with reduced production cost, reduced self-heating effects, and the resulting device.